SI53322 Datasheet, PDF (15/22 Pages) Silicon Laboratories – 1:2 LOW JITTER LVPECL CLOCK BUFFER

3. Pin Description: 16-Pin QFN
Si53322
GND 1
NC 2
NC ³
NC 4
EXPOSED
GND
PAD
12 _Q1
11 Q1
10 _Q0
9 _Q0
Figure 11. 16-QFN Pin Diagram (Top View)
Table 12. Pin Descriptions
Pin
Name Type*
1
GND
GND Ground.
Description
2
NC
— No connect. Do not connect this pin.
3
NC
— No connect. Do not connect this pin.
4
NC
— No connect. Do not connect this pin.
5
V_DD
P Core voltage supply.
Bypass with 1.0 F capacitor and place as close to the V_DD pin as possi-
ble.
6
CLK
I
Input Clock
7
CLK
I
Input clock 0 (complement)
When CLK0 is driven by a single-ended input, connect CLK0 to an
appropriate bias voltage (e.g., for a CMOS input apply V_DD/2).
8
NC
— No connect. Do not connect this pin.
9
Q0
O Output Clock 0.
10
Q0
O Output Clock 0 (complement).
11
Q1
O Output Clock 1.
12
Q1
O Output Clock 1 (complement).
13
NC
— No connect. Do not connect this pin.
Rev. 1.0
15