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SI53322 Datasheet, PDF (10/22 Pages) Silicon Laboratories – 1:2 LOW JITTER LVPECL CLOCK BUFFER | |||
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Si53322
2.3. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused outputs should be left unconnected.
VDD
DC Coupled LVPECL Termination Scheme 1
R1
R1
VDD = 3.3V or 2.5V
Si533xx
Q
50
Qn
50
3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
R2
R2
VDD
LVPECL
Receiver
VTERM = VDD â 2 V
R1 // R2 = 50 Ohm
DC Coupled LVPECL Termination Scheme 2
VDD = 3.3 V or 2.5 V
Si533xx
Q
50
Qn
50
VDD
LVPECL
Receiver
50
50
VTERM = VDD â 2V
VDD
AC Coupled LVPECL Termination Scheme 1
VDD = 3.3 V or 2.5 V
Si533xx
Q
Qn
Rb Rb
R1
0.1 uF
50
50
0.1 uF
R2
R1
VDD = 3.3 V or 2.5 V
LVPECL
Receiver
R2
VBIAS = VDD â 1.3V
R1 // R2 = 50 Ohm
3.3 V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm
2.5 V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm
AC Coupled LVPECL Termination Scheme 2
VDD = 3.3V or 2.5V
Si533xx
Q
Qn
Rb Rb
0.1 uF
50
50
0.1 uF
50
VDD = 3.3V or 2.5V
LVPECL
Receiver
50
VBIAS = VDD â 1.3 V
3.3V LVPECL: Rb = 120 Ohm
2.5V LVPECL: Rb = 90 Ohm
Figure 6. LVPECL Output Termination
10
Rev. 1.0
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