SI53322 Datasheet, PDF (1/22 Pages) Silicon Laboratories – 1:2 LOW JITTER LVPECL CLOCK BUFFER

Si53322
1:2 LOW JITTER LVPECL CLOCK BUFFER (>1.25 GHZ)
Features
 2 LVPECL outputs
 V_DD: 2.5 / 3.3 V
 Ultra-low additive jitter: 55 fs rms _{ Small size: 16-QFN (3 mm x}
 Wide frequency range: dc to
3 mm)
1250 MHz
 RoHS compliant, Pb-free
 Universal input stage accepts _{ Industrial temperature range:}
differential or LVCMOS clock
–40 to +85 °C
Applications
 High-speed clock distribution  Storage
 Ethernet switch/router
 Telecom
 Optical Transport Network (OTN)  Industrial
 SONET/SDH
 Servers
 PCI Express Gen 1/2/3
 Backplane clock distribution
Description
The Si53322 is an ultra-low-jitter two-output LVPECL buffer. Utilizing
Silicon Laboratories’ advanced fan-out clock technology, the Si53322
guarantees low additive jitter, low skew, and low propagation delay
variability from dc to 1250 MHz.
The Si53322 features minimal cross-talk and excellent supply noise
rejection, simplifying low-jitter clock distribution in noisy environments.
Functional Block Diagram
Ordering Information:
See page 17.
Pin Assignments
GND 1
NC 2
NC 3
NC 4
EXPOSED
GND
PAD
12 _Q1
11 Q1
10 _Q0
9 _Q0
VDD
CLK
CLK
Power
Supply
Filtering
Patents pending
Q0
Q0
Q1
Q1
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si53322