SI53322 Datasheet, PDF (4/22 Pages) Silicon Laboratories – 1:2 LOW JITTER LVPECL CLOCK BUFFER

Si53322
Table 4. Output Characteristics (LVPECL)
(V_DD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Output DC Common Mode
Voltage
V_COM
V_DD – 1.595
Single-Ended
V_SE
0.40
Output Swing*
*Note: Unused outputs can be left floating. Do not short unused outputs to ground.
Typ
—
0.80
Max
V_DD – 1.245
Unit
V
1.050
V
Table 5. AC Characteristics
(V_DD = 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Frequency
F
Duty Cycle
D_C
Note: 50% input duty cycle.
20/80% T_R/T_F<10% of period
(Differential input clock)
Duty Cycle
D_C
Note: 50% input duty cycle.
20/80% T_R/T_F<10% of period
(Single-Ended input clock)
Minimum Input Clock
Slew Rate
SR
Required to meet prop delay and
additive jitter specifications
(20–80%)
Output Rise/Fall Time
T_R/T_F
20–80%
Min
dc
47
45
0.75
—
Typ Max Unit
— 1250 MHz
50
53
%
50
55
%
—
— V/ns
—
350
ps
Minimum Input Pulse
Width
Propagation Delay
Output to Output Skew¹
T_W
T_PLH,
T_PHL
T_SK
360
—
—
ps
600
800 1000
ps
—
20
50
ps
Part to Part Skew²
Power Supply Noise
Rejection³
T_PS
PSRR
Differential
10 kHz sinusoidal noise
100 kHz sinusoidal noise
—
—
150
ps
—
–70
—
dBc
—
–65
—
dBc
500 kHz sinusoidal noise
—
–60
—
dBc
1 MHz sinusoidal noise
— –57.5 —
dBc
Notes:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DD (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
4
Rev. 1.0