SI5018 Datasheet, PDF (7/22 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Si5018
Table 3. AC Characteristics (Clock and Data)
(V_A 2.5 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Output Clock Rate
Output Rise/Fall Time
Clock to Data Delay
FEC (2.7 GHz)
OC-48
f_CLK
t_R,t_F
Figure 3
t_C-D
Figure 2
Input Return Loss
100 kHz–2.5 GHz
2.5 GHz–4.0 GHz
Min Typ Max Unit
2.4
—
2.7 GHz
—
80
110
ps
225
250
270
ps
225
250
270
—
16
—
dB
—
13
—
dB
Table 4. AC Characteristics (PLL Characteristics)
(V_A 2.5 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Jitter Tolerance*
J_{TOL(P–P)}
f = 600 Hz
f = 6000 Hz
40
—
—
4
—
—
f = 100 kHz
4
—
—
f = 1 MHz
.4
—
—
RMS Jitter Generation^*
J_GEN(rms) with no jitter on serial data
—
2.9
5.0
Peak-to-Peak Jitter Generation^* J_GEN(PP) with no jitter on serial data
—
25
55
Jitter Transfer Bandwidth^*
J_BW
—
—
2.0
Jitter Transfer Peaking^*
J_P
—
0.03
0.1
Acquisition Time
T_AQ
After falling edge of
1.45
1.5
1.7
PWRDN/CAL
From the return of valid data 40
60
150
Input Reference Clock Duty
Cycle
Input Reference Clock Frequency
Tolerance
Reference Clock Range
C_DUTY
C_TOL
40
50
60
–100
—
100
19.44 — 168.75
Frequency Difference at which
LOL
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
450
600
750
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
LOCK
150
300
450
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 2²³ – 1 data pattern.
Unit
UI_PP
UI_PP
UI_PP
UI_PP
mUI
mUI
MHz
dB
ms
µs
%
ppm
MHz
ppm
ppm
Rev. 1.2
7