SI5018 Datasheet, PDF (16/22 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Si5018
Pin #
15
16
17
2, 7, 11, 14
3, 8, 18, 19,
20, and
GND Pad
Table 8. Si5018 Pin Descriptions (Continued)
Pin Name
PWRDN/CAL
CLKOUT–
CLKOUT+
VDD
GND
I/O Signal Level
Description
I
LVTTL Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-
to-low transition on this pin. (See "PLL Self-Calibra-
tion‚" on page 10.)
Note: This input has a weak internal pulldown.
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
2.5 V
Supply Voltage.
Nominally 2.5 V.
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
16
Rev. 1.2