SI5018 Datasheet, PDF (12/22 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Si5018
Device Grounding
Differential Input Circuitry
The Si5018 uses the GND pad on the bottom of the 20-
pin micro leaded package (MLP) for device ground. This
pad should be connected directly to the analog supply
ground. See Figures 10 and 11 for the ground (GND)
pad location.
Bias Generation Circuitry
The Si5018 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
The Si5018 provides differential inputs for both the high
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 6. In applications where direct dc
coupling is possible, the 0.1 µF capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
voltage listed in Table 2 on page 6.
Dif f erential Driv er
0.1 µ F
Zo = 50 Ω
Si5018
D IN +,
RFCLK +
2.5 kΩ
V DD
0.1 µ F
Zo = 50 Ω
DIN –,
RFCLK –
10 kΩ
2.5 kΩ
10 kΩ
102Ω
GND
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
Clock
source
0.1 µF
Zo = 50 Ω
Si5018
2.5 kΩ
VDD
REFCLK +
100 Ω
10 kΩ
REFCLK –
0.1 µF
2.5 kΩ
10 kΩ
GND
102 Ω
Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled)
12
Rev. 1.2