SI5018 Datasheet, PDF (11/22 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Si5018
low noise and stability of the DSPLL, under the
condition where data is removed from the inputs, there
is the possibility that the PLL will not drift enough to
render an out-of-lock condition.
If REFCLK is removed, the LOL output alarm is always
asserted when it has been determined that no activity
exists on REFCLK, indicating the frequency lock status
of the PLL is unknown.
Note: LOL is not asserted during PWRDN/CAL.
PLL Performance
The PLL implementation used in the Si5018 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
The Si5018’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 4. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Jitter Transfer
The Si5018 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 5). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 4.
Jitter Generation
The Si5018 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5018 generates less than 3.0 mUI_rms of jitter when
presented with jitter free input data.
Sinusoidal
Input
Jitter (UI_PP)
15
1.5
0.15
20 dB/Decade Slope
f0 f1 f2 f3 ft
Frequency
SONET
F0
F1
F2 F3
Ft
Data Rate (Hz) (Hz) (Hz) (kHz) (kHz)
OC- 48
10 600 6000 100 1000
Figure 4. Jitter Tolerance Specification
Jitter
Trans f er
0.1 dB
A c c eptable
Range
20 dB / Dec ade
Slope
Fc
Frequenc y
S O NET
Da ta Ra te
OC- 48
Fc
(kHz )
2000
Figure 5. Jitter Transfer Specification
Powerdown
The Si5018 provides a powerdown pin, PWRDN/CAL,
that disables the output drivers (DOUT, CLKOUT).
When the PWRDN/CAL pin is driven high, the positive
and negative terminals of CLKOUT and DOUT are each
tied to VDD through 100 Ω on-chip resistors. This
feature is useful in reducing power consumption in
applications that employ redundant serial channels.
When PWRDN/CAL is released (set to low) the digital
logic resets to a known initial condition, recalibrates the
DSPLL, and will begin to lock to the data stream.
Rev. 1.2
11