SI5018 Datasheet, PDF (1/22 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Si5018
SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC
Features
Complete high-speed, low-power, CDR solution includes the following:
! Supports OC-48 /STM-16 & FEC ! Exceeds all SONET/SDH jitter
! Low power—270 mW
specifications
(typ OC-48)
! Jitter generation
! Small footprint: 4x4 mm
3.0 mUI_rms (typ)
! DSPLL™ Eliminates external ! Device powerdown
loop filter components
! Loss-of-lock indicator
! 3.3 V tolerant control inputs _{! Single 2.5 V Supply}
Ordering Information:
See page 17.
Applications
! SONET/SDH/ATM routers
! Add/drop multiplexers
! Digital cross connects
! SONET/SDH test equipment
! Optical transceiver modules
! SONET/SDH regenerators
! Board level serial links
Pin Assignments
Si5018
description
The Si5018 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/STM-16 data
rates. In addition, support for 2.7 Gbps data streams is also provided for
applications that employ forward error correction (FEC). DSPLL™
technology eliminates sensitive noise entry points thus making the PLL
less susceptible to board-level interaction and helping to ensure optimal
jitter performance.
The Si5018 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40 to 85 °C).
20 19 18 17 16
REXT 1
VDD 2
GND 3
REFCLK+ 4
REFCLK– 5
GND
Pad
Connection
15 PWRDN/CAL
14 VDD
13 DOUT+
12 DOUT–
11 VDD
6 7 8 9 10
Functional Block Diagram
LOL
DIN +
BUF
DIN – 2
D SPL L^TM
Phas e-Locked
Loop
Bias
2
R etim er
BUF
2
BUF
2
DOUT +
DOUT –
PW RDN/CAL
CLKOUT +
CLKOUT –
R EXT
Rev. 1.2 1/04
REFCLKIN +
REFCLKIN –
Copyright © 2004 by Silicon Laboratories
Si5018-DS12