SI5018 Datasheet, PDF (14/22 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC

Si5018
Differential Output Circuitry
The Si5018 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data
(DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc
coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML
architecture is listed in Table 2 on page 6.
Si5018
V DD
100 Ω
DOUT +,
CLKOUT + ^{0.1 µ F}
V DD
50 Ω
Zo = 50 Ω
DOUT –,
CLKOUT – ^{0.1 µ F}
Zo = 50 Ω
100 Ω
V DD
50 Ω
V DD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
14
Rev. 1.2