SI5010 Datasheet, PDF(7/20 Page) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SI5010 Datasheet, PDF (7/20 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

◁

Si5010

Table 3. AC Characteristics (Clock & Data)

(VA 2.5 V Â±5%, TA = â40 to 85 Â°C)

Parameter

Symbol

Output Clock Rate

Output Rise/Fall Time (differential)

Clock to Data Delay

OC-12

OC-3

fCLK

tR,tF

t(c-d)

Input Return Loss

Test Condition

Figure 3

Figure 2

100 kHzâ1 GHz

Min Typ Max Unit

.15

666 MHz

110

835

880

930

4040 4090 4140 ps

Table 4. AC Characteristics (PLL Characteristics)

(VDD = 2.5 V Â±5%, TA = â40 to 85 Â°C)

Parameter

Jitter Tolerance (OC-12 Mode)*

Symbol

JTOL(PP)

Test Condition

f = 30 Hz

f = 300 Hz

Min

Typ

Max

f = 25 kHz

Jitter Tolerance (OC-3 Mode)*

JTOL(PP)

f = 250 kHz

f = 30 Hz

f = 300 Hz

0.4

f = 6.5 kHz

f = 65 kHz

0.4

RMS Jitter Generation*

JGEN(rms) with no jitter on serial data â

1.6

3.0

Peak-to-Peak Jitter Generation

Jitter Transfer Bandwidth*

JGEN(PP) with no jitter on serial data â

JBW

OC-12 Mode

500

OC-3 Mode

130

Jitter Transfer Peaking*

f < 2 MHz

.03

0.1

Acquisition Time

TAQ

After falling edge of

1.45

1.5

1.7

PWRDN/CAL

From the return of valid

150

data

Input Reference Clock Duty Cycle

Reference Clock Range

CDUTY

19.44

155.52

Input Reference Clock Frequency

Tolerance

CTOL

â100

100

Frequency Difference at which

LOL

Receive PLL goes out of Lock

(REFCLK compared to the divided

down VCO clock)

450

600

750

Frequency Difference at which

LOCK

150

300

450

Receive PLL goes into Lock

(REFCLK compared to the divided

down VCO clock)

*Note: Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 â1 data pattern.

Unit

UIPP

mUI

kHz

Âµs

MHz

ppm

Rev. 1.3

▷