SI5010 Datasheet, PDF (12/20 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
4.10. Differential Input Circuitry
The Si5010 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is
possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with
a minimum differential peak-to-peak voltage listed in Table 2 on page 6.
Differential
Driver
0.1 µF
Zo = 50 ¬
Si5010
2.5 k¬
DIN+,
REFCLK+
VDD
0.1 µF
Zo = 50 ¬
10 k¬
DIN–,
REFCLK–
2.5 k¬
10 k¬
102 ¬
GND
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
Clock
source
0.1 µF
Zo = 50 Ω
Si5010
2.5 kΩ
VDD
REFCLK +
100 Ω
10 kΩ
REFCLK –
0.1 µF
2.5 kΩ
10 kΩ
GND
102 Ω
Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled)
Clock
source
0.1 µF
Zo = 50 Ω
100 Ω
0.1 µF
Si5010
2.5 kΩ
VDD
DIN +
10 kΩ
DIN –
2.5 kΩ
102 Ω
10 kΩ
GND
Figure 8. Single-Ended Input Termination for DIN (AC Coupled)
12
Rev. 1.3