SI5010 Datasheet, PDF (6/20 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
Table 2. DC Characteristics
(V_DD = 2.5 V ±5%, T_A = –40°C to 85°C)
Parameter
Symbol Test Condition Min
Typ
Max Unit
Supply Current
OC-12
OC-3
I_DD
—
117
131
mA
—
124
138
Power Dissipation
OC-12
OC-3
P_D
—
293
344 mW
—
310
362
Common Mode Input Voltage (DIN, REFCLK)
Single Ended Input Voltage (DIN, REFCLK)
Differential Input Voltage Swing*
(DIN, REFCLK)
V_ICM
V_IS
V_ID
varies with V_DD
See Figure 1
See Figure 1
— .80 x V_DD —
200
—
750
200
—
1500
V
mV_PP
mV_PP
Input Impedance (DIN, REFCLK)
Differential Output Voltage Swing
(DOUT)
R_IN
Line-to-Line
84
100
116
Ω
V_OD
100 Ω Load
780
970
1260 mV_PP
Line-to-Line
Differential Output Voltage Swing
(CLKOUT)
V_OD
100 Ω Load
780
970
1260 mV_PP
Line-to-Line
Output Common Mode Voltage
(DOUT,CLKOUT)
V_OCM
100 Ω Load
—
V_DD –
—
V
Line-to-Line
0.23
Output Impedance (DOUT,CLKOUT)
R_OUT Single-ended
84
100
116
Ω
Output Short to GND (DOUT,CLKOUT)
I_SC(–)
—
25
31
mA
Output Short to V_DD (DOUT,CLKOUT)
I_SC(+)
–17.5 –14.5
—
mA
Input Voltage Low (LVTTL Inputs)
V_IL
—
—
.8
V
Input Voltage High (LVTTL Inputs)
V_IH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
I_IL
—
—
10
µA
Input High Current (LVTTL Inputs)
I_IH
—
—
10
µA
Output Voltage Low (LVTTL Outputs)
V_OL
I_O = 2 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
V_OH
I_O = 2 mA
2.0
—
—
V
Input Impedance (LVTTL Inputs)
R_IN
10
—
—
kΩ
PWRDN/CAL Leakage Current
I_PWRDN V_PWRDN ≥ 0.8 V 15
25
35
µA
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (V_ID
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive
and negative input signals must exceed V_ID min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (V_IS max).
6
Rev. 1.3