SI5010 Datasheet, PDF (18/20 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
9. 4x4 mm 20L QFN Recommended PCB Layout
See Note 8
See Note 9
Gnd Pin
Symbol
Parameter
Dimensions
Min
Nom
Max
A
Pad Row/Column Width/Length
2.23
2.25
2.28
D
Thermal Pad Width/Height
2.03
2.08
2.13
e
Pad Pitch
—
0.50 BSC
—
G
Pad Row/Column Separation
2.43
2.46
2.48
R
Pad Radius
—
0.12 REF
—
X
Pad Width
0.23
0.25
0.28
Y
Pad Length
—
0.94 REF
—
Z
Pad Row/Column Extents
4.26
4.28
4.31
Notes:
1. All dimensions listed are in millimeters (mm).
2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm
separation between solder mask and pad metal, all the way around the pad.
3. The center thermal pad is to be Solder Mask Defined (SMD).
4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent
solder from flowing into the via hole.
5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a
0.65 mm pitch, should be used for the center thermal pad.
6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate
paste release.
7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended.
8. Do not place any signal or power plane vias in these “keep out” regions.
9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
18
Rev. 1.3