SI5010 Datasheet, PDF (14/20 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC

Si5010
5. Pin Descriptions: Si5010
REXT
VDD
GND
REFCLK+
REFCLK–
20 19 18 17 16
1
15
2
GND
14
3
Pad
13
4 Connection 12
5
11
6 7 8 9 10
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
Pin #
1
2, 7, 11, 14
3, 8, 18, and
GND Pad
4
5
6
9
10
Pin Name
REXT
VDD
GND
REFCLK+
REFCLK–
LOL
DIN+
DIN–
Top View
Figure 10. Si5010 Pin Configuration
Table 8. Si5010 Pin Descriptions
I/O Signal Level
Description
External Bias Resistor.
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 kΩ (1%) resis-
tor.
2.5 V
Supply Voltage.
Nominally 2.5 V.
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
I
See Table 2 ^{Differential Reference Clock.}
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
O
LVTTL
Loss-of-Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
I
See Table 2 ^{Differential Data Input.}
Clock and data are recovered from the differential
signal present on these pins.
14
Rev. 1.3