SI8900-1 Datasheet, PDF (6/30 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
Table 2. Electrical Specifications (Continued)
Parameter
Symbol Test Conditions
Min
Typ
Max Units
SPI Port Timing
EN Falling Edge to SCLK Rising
Edge
Last Clock Edge to /EN Rising
EN Falling to SDO Valid
EN Rising to SDO High-Z
SCLK High Time
SCLK Low Time
SDI Valid to SCLK Sample Edge
SCLK Sample Edge to SDI
Change
SCLK Shift Edge to SDO
Change
t_SE
t_SD
t_SEZ
t_SDZ
t_CKH
t_CKL
t_SIS
t_SIH
t_SOH
80
—
—
ns
80
—
—
ns
—
—
160
ns
—
—
160
ns
200
—
—
ns
200
—
—
ns
80
—
—
ns
80
—
—
ns
—
—
160
ns
EN
tSE
tCKL
tSD
SCLK
tCLKH
tSIS
tSIH
SDI
tSEZ
tSOH
tSDZ
SDO
Figure 1. SPI Port Timing Characteristics
6
Rev. 1.0