SI8900-1 Datasheet, PDF (21/30 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
6.2. Device Reset
During power-up, the Si890x is held in the reset state by the internal power-on reset signal (POR) until VDDA
settles above VRST. When this condition is met, a delay is initiated that maintains the Si890x in the reset state for
time period tPOR, after which the reset signal is driven high allowing the Si890x to start-up. Note the maximum
allowable VDD ramp time (i.e. time from 0 V to VDDA settled above VRST) is 1 ms. Slower ramp times may cause
the Si890x to be released from reset before VDDA reaches the VRST level.
Figure 16 shows typical VDDA monitor reset timing where the internal reset is driven low (Si890x in reset) when
VDDA falls below VRST (e.g., during a power down or VDDA brownout). The internal reset is released to its high
state when VDDA again settles above VRST. External circuitry can also be used to force a reset event by driving
the external RST input low. A 2 k pull-up resistor on RST is recommended to avoid erroneous reset events from
external noise coupling to the RST input.
VRSTH
VRSTL
VDDA
VDDA(min)
Internal
RESET
tPOR
Power‐On Reset
VDDA
Monitor
Reset
Figure 16. Si890x Power-on and Monitor Reset
Rev. 1.0
21