SI8900-1 Datasheet, PDF (12/30 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
The Burst Mode ADC transactions for the Si8900 (Figure 6A) and Si8901 (Figure 6B) are substantially the same. A
Burst Mode ADC read is initiated when the master writes a CNFG_0 (MODE = 0) Command Byte to the Si8900/1,
which updates the CNFG_0 register and triggers the ADC continuously. Like the Demand Mode example, the
Si8901 has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must
write the I²C port address prior to reading the serial port. The Si8902 Burst Mode (Figure 6C) is similar to that of
the Si8900/1, except the master must wait 8 µs before reading the first Burst Mode ADC data packet. After reading
the first Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay.
Master to Slave
Slave to Master
Master writes CNFG_0
Command Byte to Si8900 Rx
CNFG_0
Command
Byte 0
MODE = 0 _tCONV
tCONV
tCONV
CNFG_0
Command
Byte
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
Master reads updated CNFG_0 Command Byte and ADC data from Si8900 Tx
A) Si8900 ADC Burst Mode (MODE = 0)
Master writes Slave Address & CNFG_0
Command Byte to Si8901 SDA
Slave Addrress
Write
CNFG_0
Command
Byte 0
MODE = 0
Master to Slave
Slave to Master
Slave Address
Read
tCONV
CNFG_0
Command
Byte
ADC_H
Data
tCONV
ADC_L
Data
ADC_H
Data
tCONV
ADC_L
Data
Master reads Slave Address, updated CNFG_0 and ADC data from Si8901 SDA
B) Si8901 ADC Burst Mode (MODE = 0)
Master writes CNFG_0 Command
Byte to Si8902 SDI
Master to Slave
Slave to Master
CNFG_0
Command
Byte
MODE = 0
tCONV
tCONV
tCONV
CNFG_0
Command
Byte
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
Master reads updated CNFG_0 and ADC data from Si8902 SDO
C) Si8902 ADC Burst Mode (MODE = 0)
Figure 6. ADC Burst Mode Operation
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Rev. 1.0