SI8900-1 Datasheet, PDF (16/30 Pages) Silicon Laboratories – ISOLATED MONITORING ADC

Si8900/1/2
4.3. SPI Port (Si8902)
EN
SCLK
SDI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Figure 13. Si8902 Data/Clock Timing
The Serial Peripheral Interface (SPI port) is a slave mode, full-duplex, synchronous, 4-wire serial bus that connects
to the master as shown in Figure 12. The master's clock and data timing must match the Si8902 timing shown
Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on
page 6).
As shown in Figure 13, an SPI bus transaction begins with the master driving EN low and maintaining this state for
the duration of the read transaction(s). The master transmits data from its master-out/slave-in terminal (MOSI) to
the Si8902 serial read/write input terminal (SDI). The Si8902 transmits data to the master from its serial data-out
terminal (SDO) to the master-in/slave-out terminal (MISO), and data transfer ends when the master returns /EN to
the high state. Figure 14A shows the Si8902 CNFG_0 Command Byte format, while Figures 14B and 14C show
Si8902 Demand Mode and Burst Mode ADC reads.
16
Rev. 1.0