SI8410BB-D-IS Datasheet, PDF (6/30 Pages) Silicon Laboratories – LOW-POWER SINGLE AND DUAL-CHANNEL DIGITAL ISOLATORS

Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(V_DD1 = 5 V ±10%, V_DD2 = 5 V ±10%, T_A = –40 to 125 ºC)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
V_DD1
V_DD2
—
1.3
2.0
mA
—
1.2
1.8
Si8420Bx
V_DD1
—
2.0
3.0
mA
V_DD2
—
2.1
3.2
Si8421Bx
d ^VDD1
V_DD2
—
2.2
3.3
mA
—
2.2
3.3
e _{100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)}
d _Si8410Bx
V_DD1
n _{s VDD2}
e _{n Si8420Bx}
V_DD1
m _ig ^VDD2
Si8421Bx
m ^{s VDD1}
o ^{e VDD2}
—
—
—
—
—
—
Timing Characteristics
1.4
2.1
mA
4.6
5.8
2.2
3.3
mA
9.2
11.5
5.8
7.3
mA
5.8
7.3
c ^D Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
1.0 Mbps
e _{w Minimum Pulse Width}
—
—
250
ns
R _{Propagation Delay}
t_PHL, t_PLH See Figure 1
—
—
35
ns
t ^{e Pulse Width Distortion}
o ^{N |tPLH - tPHL|}
PWD
See Figure 1
—
Propagation Delay Skew²
t_PSK(P-P)
—
—
25
ns
—
40
ns
N ^{r Channel-Channel Skew}
t_PSK
—
—
35
ns
fo ^Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t_PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.5