SI8410BB-D-IS Datasheet, PDF (23/30 Pages) Silicon Laboratories – LOW-POWER SINGLE AND DUAL-CHANNEL DIGITAL ISOLATORS

Si8410/20/21
3. Errata and Design Migration Guidelines
The following errata apply to Revision C devices only. See "5. Ordering Guide" on page 25 for more details. No
errata exist for Revision D devices.
3.1. Power Supply Bypass Capacitors (Revision C and Revision D)
When using the Si84xx isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.1.1. Resolution
For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 20. Additionally, refer to "5.
Ordering Guide" on page 25 for current ordering information.
d _{3.2. Latch Up Immunity (Revision C Only)}
e _{Si84xx latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-}
d up immunity. To increase latch-up immunity on these pins, 100  of equivalent resistance must be included in
series with all of the pins listed in Table 13. The 100  equivalent resistance can be comprised of the source
n _{s driver's output resistance and a series termination resistor. The Si8410 is not affected by the latch up immunity}
e ^{issue described above.}
n _{3.2.1. Resolution}
m _ig ^{This issue has been corrected with Revision D of the device. Refer to “5. Ordering Guide” for current ordering}
information.
m ^s _{Table 13. Affected Ordering Part Numbers (Revision C Only)}
co ^{De Affected Ordering Part Numbers*}
Device
Revision
e _{SI8420SV-C-IS, SI8421SV-C-IS}
C
Not ^{Rfor New *Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB).}
Pin#
3
7
Name
A2
B1
Pin Type
Input or Output
Output
Rev. 1.5
23