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SI554 Datasheet, PDF (6/15 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL | |||
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Si554
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Phase Jitter (RMS)1,2,5
for FOUT 10 to 160 MHz
CMOS Output Only
Symbol
Test Condition
Min
ï¦J Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
â
50 kHz to 20 MHz
â
Typ
0.63
0.62
Max Units
â
ps
â
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
â
0.63
â
ps
50 kHz to 20 MHz
â
0.62
â
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
â
0.67
â
ps
50 kHz to 20 MHz
â
0.66
â
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
â
0.74
â
ps
50 kHz to 20 MHz
â
0.72
â
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
â
0.83
â
ps
50 kHz to 20 MHz
â
0.8
â
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
â
1.26
â
ps
50 kHz to 20 MHz
â
1.2
â
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the applicationâs minimum APR
requirements. See âAN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)â for more information.
3. See âAN255: Replacing 622 MHz VCSO devices with the Si550 VCXOâ for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 6. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Period Jitter*
JPER
RMS
Peak-to-Peak
â
2
â
ps
â
14
â
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
6
Rev. 1.1
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