SI554 Datasheet, PDF (2/15 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

Si554
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
Typ
Max Units
Supply Voltage¹
3.3 V option
V_DD
2.5 V option
1.8 V option
2.97
3.3
3.63
V
2.25
2.5
2.75
V
1.71
1.8
1.89
V
Supply Current
Output enabled
LVPECL
—
120
130
CML
I_DD
LVDS
—
108
117
mA
—
99
108
CMOS
—
90
98
Tristate mode
—
60
75
mA
Output Enable (OE)
and Frequency Select FS[1:0]²
V_IH
0.75 x V_DD
—
—
V
V_IL
—
—
0.5
V
Operating Temperature Range
T_A
–40
—
85
ºC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.
2. OE and FS[1:0] pins include a 17 k resistor to VDD.
Table 2. V_C Control Voltage Input
Parameter
Symbol Test Condition
Min
Typ
Max Units
Control Voltage Tuning Slope^1,2,3
10 to 90% of V_DD
—
33
—
ppm/V
45
90
K_V
135
180
356
Control Voltage Linearity⁴
BSL
–5
±1
+5
%
L_VC
Incremental
–10
±5
+10
%
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
V_C Input Impedance
Z_VC
500
—
—
k
Nominal Control Voltage
V_CNOM
@ f_O
—
V_DD/2
—
V
Control Voltage Tuning Range
V_C
0
V_DD
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
3. K_V variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V_C ranging from 10 to 90% of V_DD. Incremental slope
determined with V_C ranging from 10 to 90% of V_DD.
2
Rev. 1.1