SI554 Datasheet, PDF (3/15 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

Si554
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min Typ Max Units
Nominal Frequency^1,2,3
Temperature Stability^1,4
Absolute Pull Range^1,4
f_O
APR
LVDS/CML/LVPECL
CMOS
T_A = –40 to +85 °C
10
—
945 MHz
10
—
160 MHz
–20
—
+20
–50
—
+50 ppm
–100
—
+100
±12
—
±375 ppm
Aging
Power up Time⁵
Settling Time After FS[1:0]
Change
Frequency drift over first year.
—
Frequency drift over 15 year life. —
t_OSC
—
t_FRQ Both FS[1] and FS[0] changing
—
simultaneously
—
±3
ppm
—
±10
—
10
ms
—
20
ms
Notes:
1. See Section 3. "Ordering Information" on page 10 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by V_CNOM = V_DD/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to f_O (to within ±1 ppm of f_O).
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option¹
LVDS Output Option²
Symbol
V_O
V_OD
V_SE
V_O
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
Min
V_DD – 1.42
1.1
0.55
1.125
Typ
—
—
—
1.20
Max Units
V_DD – 1.25 V
1.9
V_PP
0.95
V_PP
1.275
V
V_OD
swing (diff)
0.5
0.7
0.9
V_PP
CML Output Option²
2.5/3.3 V option mid-level
V_O
1.8 V option mid-level
—
V_DD – 1.30
—
—
V_DD – 0.36
—
V
V
CMOS Output Option³
Rise/Fall time (20/80%)
Symmetry (duty cycle)
V_OD
V_OH
V_OL
t_R, t_F
SYM
Notes:
1. 50  to V_DD – 2.0 V.
2. R_term = 100  (differential).
3. C_L = 15 pF
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
I_OH = 32 mA
I_OL = 32 mA
LVPECL/LVDS/CML
CMOS with C_L = 15 pF
LVPECL:
(diff)
V_DD – 1.3 V
LVDS:
1.25 V (diff)
CMOS:
V_DD/2
1.10
0.35
0.8 x V_DD
—
—
—
45
1.50
0.425
—
—
—
1
—
1.90
V_PP
0.50
V_PP
V_DD
V
0.4
350
ps
—
ns
55
%
Rev. 1.1
3