SI554 Datasheet, PDF (5/15 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

Si554
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Phase Jitter (RMS)^1,2,3,4,5
for F_OUT of 125 to 500 MHz
Symbol
Test Condition
Min
_J Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
—
50 kHz to 80 MHz (OC-192) _—
Typ
0.37
0.33
Max Units
—
ps
—
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
—
50 kHz to 80 MHz (OC-192) —
0.37
0.33
0.4
ps
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.43
—
ps
50 kHz to 80 MHz (OC-192) _—
0.34
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.50
—
ps
50 kHz to 80 MHz (OC-192) _—
0.34
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
—
0.59
—
ps
50 kHz to 80 MHz (OC-192) —
0.35
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
—
1.00
—
ps
50 kHz to 80 MHz (OC-192) _—
0.39
—
Notes:
1. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Max jitter for LVPECL output with V_C=1.65V, V_DD=3.3V, 155.52 MHz.
5. Max offset frequencies: 80 MHz for F_OUT > 250 MHz, 20 MHz for 50 MHz < F_OUT <250 MHz,
2 MHz for 10 MHz < F_OUT <50 MHz.
Rev. 1.1
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