SI554 Datasheet, PDF (1/15 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

Si554
REVISION D
QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ
Features
 Available with any-rate output
 Internal fixed crystal frequency
frequencies from 10–945 MHz and
ensures high reliability and low
selected frequencies to 1.4 GHz
aging
 Four selectable output frequencies  Available CMOS, LVPECL,
 3rd generation DSPLL^® with superior ^{LVDS, and CML outputs}
jitter performance
 3.3, 2.5, and 1.8 V supply options
 3x better frequency stability than ^{ Industry-standard 5 x 7 mm}
SAW-based oscillators
package and pinout
 Pb-free/RoHS-compliant
Applications
 SONET/SDH
 xDSL
 10 GbE LAN / WAN
Description
 Low jitter clock generation
 Optical modules
 Clock and data recovery
The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL^® circuitry to provide a very low jitter clock for all output frequencies.
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory-programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
VDD
CLK- CLK+
Si5602
Ordering Information:
See page 10.
Pin Assignments:
See page 9.
(Top View)
FS[1]
V_{C 1}
7
6 VDD
OE 2
5 CLK–
GND 3
4
8
FS[0]
CLK+
Any-rate
FS1
Fixed
Frequency XO
10–1400 MHz
DSPLL^®
FS0
Clock Synthesis
ADC
Rev. 1.1 4/13
Vc
OE
GND
Copyright © 2013 by Silicon Laboratories
Si554