SI53156 Datasheet, PDF (5/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53156
Table 2. AC Electrical Specifications
Parameter
Symbol
Condition
Min Typ
DIFFIN at 0.7 V
Input Frequency Range
f_in
100 —
Rising and Falling Slew Rates for T_R/T_F
Single ended measurement: 0.6
—
Each Clock Output Signal in a
V_OL = 0.175 to V_OH = 0.525 V
Given Differential Pair
(Averaged)
Differential Input High Voltage
Differential Input Low Voltage
Crossing Point Voltage at 0.7 V
Swing
V_IH
150 —
V_IL
—
—
V_OX
Single-ended measurement 250 —
Vcross Variation over all edges
V_OX
Single-ended measurement
—
—
Differential Ringback Voltage
V_RB
–100 —
Time before ringback allowed
T_STABLE
500 —
Absolute maximum input voltage V_MAX
—
—
Absolute minimum input voltage
V_MIN
–0.3 —
Duty Cycle for Each Clock Output T_DC Measured at crossing point V_OX 45
—
Signal in a Given
Differential Pair
Rise/Fall Matching
DIFF at 0.7 V
T_RFM
Determined as a fraction of
2 x (T_R – T_F)/(T_R + T_F)
—
—
Duty Cycle
Clock Skew
Additive Peak Jitter
T_DC
Measured at 0 V differential
45
—
T_SKEW
Measured at 0 V differential
—
—
Pk-Pk
0
—
Additive PCIe Gen 2 Phase Jitter RMS_GEN2
10 kHz < F < 1.5 MHz
0
—
1.5 MHz< F < Nyquist Rate
0
—
Additive PCIe Gen 3 Phase Jitter RMS_GEN3 Includes PLL BW 2–4 MHz
0
—
(CDR = 10 MHz)
Additive PCIe Gen 4 Phase Jitter RMS_GEN4
PCIe Gen 4
—
—
Additive Cycle to Cycle Jitter
T_CCJ
Measured at 0 V differential
—
—
Long-term Accuracy
L_ACC
Measured at 0 V differential
—
—
Rising/Falling Slew rate
T_R / T_F
Measured differentially from
2.5
—
±150 mV
Crossing Point Voltage at 0.7 V
V_OX
Swing
300 —
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Max Unit
210 MHz
4
V/ns
—
mV
–150 mV
550 mV
140 mV
100 mV
—
ps
1.15
V
—
V
55
%
20
%
55
%
50
ps
10
ps
0.5
ps
0.5
ps
0.10 ps
0.10 ps
50
ps
100 ppm
8
V/ns
550 mV
Rev. 1.1
5