SI53156 Datasheet, PDF (16/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53156
Pin #
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Name
DIFF1
VDD
DIFF2
DIFF2
VDD
DIFF3
DIFF3
DIFF4
DIFF4
VDD
DIFF5
DIFF5
VDD
SCLK
SDATA
CKPWRGD_PDB
VDD
DIFFIN
DIFFIN
OE0
OE1
GND
Table 6. Si53156 32-Pin QFN Descriptions
Type
Description
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
I SMBus compatible SCLOCK.
I/O SMBus compatible SDATA.
I, PU
3.3 V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. A real-time
active low input for asserting power down (PDB) and disabling all outputs
(internal 100 k pull-up).
PWR 3.3 V power supply.
I
0.7 V Differential True Input, typically 100 MHz. Input frequency range
100 to 210 MHz.
O
0.7 V Differential Complement Input, typically 100 MHz. Input frequency
range 100 to 210 MHz.
I,PU
Active high input pin enables DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU
Active high input pin enables DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
GND Ground for bottom pad of the IC.
16
Rev. 1.1