SI53156 Datasheet, PDF (1/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53156
PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4
FANOUT BUFFER
Features
 PCI-Express Gen 1, Gen 2, Gen 3,  Six PCI-Express buffered clock
and Gen 4 common clock compliant outputs
 Supports Serial ATA (SATA) at
 Clock input spread tolerable
100 MHz
 Supports LVDS outputs
 100–210 MHz operation
 I²C support with readback
 Low power, push pull, differential
capabilities
output buffers
 Extended temperature:


Internal termination for maximum
integration

Dedicated
output
output
enable
pin
for
each

–40 to 85 ^oC
3.3 V power supply
32-pin QFN package
Applications
 Network attached storage
 Multi-function printers
 Wireless access point
 Routers
Description
The Si53156 is a spread spectrum tolerant PCIe clock buffer that can source six
PCIe clocks simultaneously. The device has six hardware output enable control
inputs for enabling the respective differential outputs on the fly. The device also
features output enable control through I²C communication. I²C programmability is
also available to dynamically control skew, edge rate and amplitude on the true,
compliment, or both differential signals on the clock outputs. This control feature
enables optimal signal integrity as well as optimal EMI signature on the clock
outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe
Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Functional Block Diagram
Ordering Information:
See page 17.
Pin Assignments
32 31 30 29 28 27 26 25
VDD 1
24 VDD
OE2* 2
23 DIFF5
VDD 3
OE3* 4
OE4* 5
33
GND
22 DIFF5
21 VDD
20 DIFF4
OE5* 6
19 DIFF4
NC 7
18 DIFF3
VDD 8
17 DIFF3
9 10 11 12 13 14 15 16
*Note: Internal 100 kohm pull-up.
DIFFIN
DIFFIN
SCLK
SDATA
OE [5:0]
Control & Memory
Control RAM
DIFF0
DIFF1
DIFF2
DIFF3
DIFF4
DIFF5
Patents pending
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53156