SI53156 Datasheet, PDF (18/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53156
7. Package Outline
Figure 5 illustrates the package details for the Si53156. Table 7 lists the values for the dimensions shown in the
illustration.
Figure 5. 32-Pin Quad Flat No Lead (QFN) Package
Table 7. Package Diagram Dimensions
Dimension
A
Min
Nom
Max
0.70
0.75
0.80
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
5.00 BSC
D2
3.15
3.20
3.25
e
0.50 BSC
E
5.00 BSC
E2
3.15
3.20
3.25
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
4. Coplanarity less than 0.08 mm.
5. Terminal #1 identifier and terminal numbering convention conform to JESD 95-1 SPP-012.
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Rev. 1.1