SI53154 Datasheet, PDF (5/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD FANOUT BUFFER

Si53154
Table 2. AC Electrical Specifications
Parameter
DIFFIN at 0.7 V
Symbol
Condition
Min Typ Max Unit
Input Frequency Range
f_in
100
—
210 MHz
Rising and Falling Slew
T_R / T_F Single ended measurement: V_OL = 0.6
—
Rates for Each Clock Output
0.175 to V_OH = 0.525 V (Averaged)
Signal in a Given Differential
Pair
4 V/ns
Differential Input High
V_IH
Voltage
150
—
— mV
Differential Input Low
V_IL
Voltage
—
—
–150 mV
Crossing Point Voltage at
V_OX
Single-ended measurement
250
—
550 mV
0.7 V Swing
Vcross Variation over all
Edges
V_OX
Single-ended measurement
—
—
140 mV
Differential Ringback Voltage V_RB
–100
—
100 mV
Time before Ringback
Allowed
T_STABLE
500
—
— ps
Absolute Maximum Input
Voltage
V_MAX
—
—
1.15 V
Absolute Minimum Input
Voltage
V_MIN
–0.3
—
—
V
Duty Cycle for Each Clock
T_DC
Measured at crossing point V_OX
45
—
55 %
Output Signal in a Given
Differential Pair
Rise/Fall Matching
T_RFM
Determined as a fraction of
2 x (T_R – T_F)/(T_R + T_F)
—
—
20 %
DIFF at 0.7 V
Duty Cycle
Clock Skew
Additive Peak Jitter
T_DC
T_SKEW
Pk-Pk
Measured at 0 V differential
Measured at 0 V differential
45
—
55 %
—
—
50 ps
0
—
10 ps
Additive PCIe Gen 2 Phase RMS_GEN2
Jitter
10 kHz < F < 1.5 MHz
1.5 MHz< F < Nyquist Rate
0
—
0.5 ps
0
—
0.5 ps
Additive PCIe Gen 3 Phase RMS_GEN3
Jitter
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
0
—
0.10 ps
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.1
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