SI53154 Datasheet, PDF (10/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD FANOUT BUFFER

Si53154
4. Control Registers
4.1. I²C Interface
To enhance the flexibility and function of the clock buffer, an I²C interface is provided. Through the I²C Interface,
various device functions are available, such as individual clock output enable. The registers associated with the I²C
Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register
changes are normally made at system initialization, if any are required. Power management functions can only be
programed in program mode and not in normal operation modes.
4.2. Data Protocol
The I²C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block
write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller
can access individually indexed bytes.
The block write and block read protocol is outlined in Table 4 while Table 5 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Block Read Protocol
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
10
Rev. 1.1