SI53154 Datasheet, PDF (1/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD FANOUT BUFFER

Si53154
PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD
FANOUT BUFFER
Features
 PCI-Express Gen 1, Gen 2, Gen 3,  Four PCI-Express buffered clock
and Gen 4 common clock
outputs
compliant
 Clock input spread tolerable
 Supports Serial ATA (SATA) at _{ Supports LVDS outputs}
100 MHz
 I²C support with readback
 100–210 MHz operation
capabilities
 Low power, push pull, differential _{ Extended temperature:}

output buffers
Internal termination for maximum
integration

–40 to 85 ^oC
3.3 V power supply
 Dedicated output enable pin for ^{ 24-pin QFN package}
each output
Applications
 Network attached storage
 Multi-function printers
 Wireless access point
 Routers
Description
The Si53154 is a spread spectrum tolerant PCIe clock buffer that can source
four PCIe clocks simultaneously. The device has four hardware output enable
control inputs for enabling the respective differential outputs on the fly. The
device also features output enable control through I²C communication. I²C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at www.silabs.com/pcie-learningcenter.
Functional Block Diagram
Ordering Information:
See page 17.
Pin Assignments
VDD 1
OE1* 2
VDD 3
VSS 4
OE2* 5
VDD 6
24 23 22 21 20 19
18 OE3*
17 VDD
25
GND
16 DIFF3
15 DIFF3
14 DIFF2
13 DIFF2
7 8 9 10 11 12
*Note: Internal 100 kohm pull-up.
Patents pending
DIFFIN
DIFFIN
SCLK
SDATA
OE [3:0]
Control & Memory
Control RAM
DIFF0
DIFF1
DIFF2
DIFF3
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53154