SI53154 Datasheet, PDF (18/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 QUAD FANOUT BUFFER

Si53154
7. Package Outline
Figure 5 illustrates the package details for the Si53154. Table 7 lists the values for the dimensions shown in the
illustration.
Figure 5. 24-Pin Quad Flat No Lead (QFN) Package
Table 7. Package Diagram Dimensions
Symbol
Millimeters
Min
Nom
Max
A
0.70
0.75
0.80
A1
0.00
0.025
0.05
b
0.20
0.25
0.30
D
4.00 BSC
D2
2.60
2.70
2.80
e
0.50 BSC
E
4.00 BSC
E2
2.60
2.70
2.80
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.07
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components
18
Rev. 1.1