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SI53303 Datasheet, PDF (4/30 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR | |||
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Si53303
Table 3. DC Common Characteristics
(VDD = 1.8 V ï±ï 5%, 2.5 V ï± 5%, or 3.3 V ï±ï 10%,TA = â40 to 85 ï°C)
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz
Symbol
IDD
IDDOX
Test Condition
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load (3.3 V)
Leakage Current
Voltage Reference
Input High Voltage
IL
VREF
VIH
CMOS (1.8 V, SFOUT = Open/0),
per output, CL = 5 pF, 200 MHz
CMOS (2.5 V, SFOUT=Open/0),
per output, CL=5pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, CL = 5 pF, 200 MHz
Input leakage at all inputs except
CLKIN, VIN = 0 V
Input leakage at CLKIN
VIN = 0 V
VREF pin
SFOUTX, DIVX
3-level input pins
Input Mid Voltage
VIM
SFOUTX, DIVX
3-level input pins
Input Low Voltage
VIL
SFOUTX, DIVXpin
3-level input pins
Internal Pull-down
Resistor
RDOWN CLK_SEL, DIVA, DIVB, SFOUTA[1],
SFOUTB[1]
Internal Pull-up
Resistor
RUP
SFOUTA[1], SFOUTB[1], DIVA,
DIVB, OEA, OEB
Min
â
â
â
â
â
â
â
â
â
â
â
â
0.85 x
VDD
0.45 x
VDD
â
â
â
Typ
TBD
35
30
20
30
35
5
8
15
â
â
VDD/2
â
0.5 x
VDD
â
25
25
Max
100
â
â
â
â
â
â
â
â
TBD
TBD
â
â
0.55 x
VDD
0.15 x
VDD
â
â
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
kâ¦
kâ¦
4
Preliminary Rev. 0.4
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