SI53303 Datasheet, PDF (22/30 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR

Si53303
3. Pin Description: 44-Pin QFN
DIVA 1
SFOUTA[1] ²
SFOUTA[0] 3
Q2 ⁴
Q2 ⁵
GND ⁶
Q1 ⁷
Q1 ⁸
Q0 ⁹
Q0 ¹⁰
NC ¹¹
GND
PAD
33 _DIVB
32 _SFOUTB[1]
31 _SFOUTB[0]
30 _Q7
29 _Q7
28 NC
27 _Q8
26 _Q8
25 _Q9
24 _Q9
23 _NC
Pin #
1
2
3
4
5
6
7
8
Name
DIVA
SFOUTA[1]
SFOUTA[0]
Q2
Q2
GND
Q1
Q1
Table 19. Pin Description
Description
Output divider control pin for Bank A
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or V_DD.
Output signal format control pin for Bank A
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or V_DD.
Output signal format control pin for Bank A
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or V_DD.
Output clock 2 (complement)
Output clock 2
Ground
Output clock 1 (complement)
Output clock 1
22
Preliminary Rev. 0.4