SI53303 Datasheet, PDF (14/30 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR

Si53303
2.5. Flexible Output Divider
The Si53303 provides optional clock division in addition to clock distribution. The divider setting for each bank of
output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVX pins open will force
a divider value of 1 which is the default mode of operation.
Table 15. Divider Selection
DIVX
Open*
Divider Value
1 (default)
0
2
1
4
*Note: DIVX are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to
V_DD/2.
2.6. Output Enable Logic
Each 1:5 output has an independent clock input (CLK0/CLK1) and an output enable pin. The table below
summarizes the input and output clock based upon the state of the input clock and the OE pin.
Table 16. Input Clock and Output Enable Logic
CLK
OE¹
Q²
L
H
L
H
H
H
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition
of CLK0 or CLK1.
3. Single-end: Q=low, Q=high
Differential: Q=low, Q=high
2.7. Power Supply (V_DD and V_DDOX)
The device includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to
operate at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD
supports 3.3V, 2.5V, or 1.8V. Each output bank has its own V_DDOX supply, supporting 3.3V, 2.5V, or 1.8V.
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Preliminary Rev. 0.4