SI53303 Datasheet, PDF (23/30 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR

Pin #
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
Q0
Q0
NC
VDD
NC
CLK0
CLK0
OEA
V_REF
OEB
CLK1
CLK1
NC
GND
NC
Q9
Q9
Q8
Q8
NC
Si53303
Table 19. Pin Description (Continued)
Output clock 0 (complement)
Description
Output clock 0
No connect
Core voltage supply
Bypass with 1.0 µF capacitor and place close to the VDD pin as possible
No connect
Input clock 0
Input clock 0 (complement)
When CLK0 is driven by a single-end input, connect V_REF to CLK0
CLK0 contains an internal pull-up resistor
Output enable—Bank A
When OE = high, the Bank A outputs are enabled
When OE = low, Q is held low and Q is held high for differential formats
For LVCMOS, both Q and Q are held low when OE is set low
OEA contains an internal pull-up resistor
Input reference voltage
When driven by a LVCMOS clock input, connect the unused clock input to V_REF and a
0.1µF cap to ground. When driven by a differential clock, do not connect the V_REF pin.
Output enable—Bank B
When OE = high, the Bank B outputs are enabled
When OE = low, Q is held low and Q is held high for differential formats
For LVCMOS, both Q and Q are held low when OE is set low
OEB contains an internal pull-up resistor.
Input clock 1
Input clock 1 (complement)
When CLK1 is driven by a single-end input, connect V_REF to CLK1
CLK1 contains an internal pull-up resistor
No connect
Ground
No connect
Output clock 9 (complement)
Output clock 9
Output clock 8 (complement)
Output clock 8
No connect
Preliminary Rev. 0.4
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