SI53303 Datasheet, PDF (1/30 Pages) Silicon Laboratories – DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR

Si53303
DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR
Features
 10 differential or 20 LVCMOS outputs Independent V_DD and V_DDO :
 Ultra-low additive jitter: 100 fs rms
1.8/2.5/3.3 V
 Wide frequency range: 1 to 725 MHz Excellent power supply noise
 Any-format input with pin selectable rejection (PSRR)
output formats: LVPECL, Low Power  Selectable LVCMOS drive strength to
LVPECL, LVDS, CML, HCSL,
tailor jitter and EMI performance
LVCMOS
 Small size: 44-QFN (7 mm x 7 mm)
 Synchronous output enable
 RoHS compliant, Pb-free
 Output clock division: /1, /2, /4
 Industrial temperature range:
 Low output-output skew: <50 ps
–40 to +85 °C
 Low propagation delay variation:
<400 ps
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53303 is an ultra low jitter dual 1:5 differential output buffer with pin-
selectable output clock signal format and divider selection. The Si53303 utilizes
Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to
725 MHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53303 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 25.
Pin Assignments
Si53303
DIVA 1
SFOUTA[1] 2
SFOUTA[0] 3
Q2 4
Q2 ⁵
GND 6
Q1 7
Q1 8
Q0 ⁹
Q0 ¹⁰
NC 11
GND
PAD
33 DIVB
32 _SFOUTB[1]
31 _SFOUTB[0]
30 _Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 NC
Patents pending
VRE F
CLK0
CLK0
Vref
Generator
Power
Supply
Filtering
DivA
CLK1
CLK1
DivB
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
DIVB
VDDOB
SF OU TB [1:0]
OEB
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53303
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.