EFM8BB1 Datasheet, PDF (4/46 Pages) Silicon Laboratories – The EFM8BB1 highlighted features are listed below

3. System Overview
3.1 Introduction
EFM8BB1 Data Sheet
System Overview
C2CK/RSTb
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core
8/4/2 KB ISP Flash
Program Memory
256 Byte SRAM
256 Byte XRAM
VDD
GND
Power Net
Independent
Watchdog Timer
SYSCLK
SFR
Bus
System Clock
Configuration
EXTCLK
24.5 MHz
2%
Oscillator
Low-Freq.
Oscillator
CMOS
Oscillator
Input
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
3-ch PCA
I2C /
SMBus
SPI
CRC
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Internal
Reference
VDD
VREF
12/10 bit
ADC
VDD
Temp
Sensor
+-+-
2 Comparators
Port 0
Drivers
Port 1
Drivers
Port 2
Driver
P0.n
P1.n
P2.n
Figure 3.1. Detailed EFM8BB1 Block Diagram
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