EFM8BB1 Datasheet, PDF (14/46 Pages) Silicon Laboratories – The EFM8BB1 highlighted features are listed below

EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol Test Condition
Min
Typ
Conversion Time
t_CNV
10-Bit Conversion,
1.1
SAR Clock = 12.25 MHz,
System Clock = 24.5 MHz.
Sample/Hold Capacitor
C_SAR
Gain = 1
Gain = 0.5
—
5
—
2.5
Input Pin Capacitance
Input Mux Impedance
Voltage Reference Range
Input Voltage Range*
C_IN
R_MUX
V_REF
V_IN
Gain = 1
Gain = 0.5
—
20
—
550
1
—
0
—
0
—
Power Supply Rejection Ratio
DC Performance
PSRR_ADC
—
70
Integral Nonlinearity
INL
12 Bit Mode
—
±1
10 Bit Mode
—
±0.2
Differential Nonlinearity (Guaran- DNL
teed Monotonic)
12 Bit Mode
10 Bit Mode
–1
±0.7
—
±0.2
Offset Error
E_OFF
12 Bit Mode, VREF = 1.65 V
10 Bit Mode, VREF = 1.65 V
–3
0
–2
0
Offset Temperature Coefficient
Slope Error
TC_OFF
E_M
12 Bit Mode
10 Bit Mode
—
0.004
—
±0.02
—
±0.06
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput, using AGND pin
Signal-to-Noise
SNR
12 Bit Mode
61
66
10 Bit Mode
53
60
Signal-to-Noise Plus Distortion
SNDR
12 Bit Mode
61
66
10 Bit Mode
53
60
Total Harmonic Distortion (Up to
5th Harmonic)
THD
12 Bit Mode
10 Bit Mode
—
71
—
70
Spurious-Free Dynamic Range
SFDR
12 Bit Mode
—
–79
10 Bit Mode
—
–74
Note:
1. Absolute input pin voltage is limited by the V_DD supply.
Max
Unit
µs
—
pF
—
pF
—
pF
—
Ω
V_DD
V
V_REF
V
2xV_REF
V
—
dB
±2.3
±0.6
1.9
±0.6
3
2
—
±0.1
±0.24
LSB
LSB
LSB
LSB
LSB
LSB
LSB/°C
%
%
—
dB
—
dB
—
dB
—
dB
—
dB
—
dB
—
dB
—
dB
Table 4.8. Voltage Reference
Parameter
Internal Fast Settling Reference
Symbol Test Condition
Min
Typ
Max
Unit
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