EFM8BB1 Datasheet, PDF (12/46 Pages) Silicon Laboratories – The EFM8BB1 highlighted features are listed below

EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Note:
1. Currents are additive. For example, where I_DD is specified and the mode is not mutually exclusive, enabling the functions increa-
ses supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
V_DD Supply Monitor Threshold
V_VDDM
Power-On Reset (POR) Threshold V_POR
V_DD Ramp Time
t_RMP
Reset Delay from POR
t_POR
Reset Delay from non-POR source t_RST
RST Low Time to Generate Reset t_RSTL
Missing Clock Detector Response t_MCD
Time (final rising edge to reset)
Missing Clock Detector Trigger
Frequency
F_MCD
V_DD Supply Monitor Turn-On Time t_MON
Test Condition
Rising Voltage on V_DD
Falling Voltage on V_DD
Time to V_DD ≥ 2.2 V
Relative to V_DD ≥ V_POR
Time between release of reset
source and code execution
F_SYSCLK > 1 MHz
Table 4.4. Flash Memory
Min
Typ
Max
Unit
1.85
1.95
2.1
V
—
1.4
—
V
0.75
—
1.36
V
10
—
—
µs
3
10
31
ms
—
39
—
µs
15
—
—
µs
—
0.625
1.2
ms
—
7.5
13.5
kHz
—
2
—
µs
Parameter
Symbol Test Condition
Min
Typ
Max
Units
Write Time^{1 ,2}
t_WRITE
One Byte,
F_SYSCLK = 24.5 MHz
19
20
21
µs
Erase Time^{1 ,2}
t_ERASE
One Page,
F_SYSCLK = 24.5 MHz
5.2
5.35
5.5
ms
V_DD Voltage During Programming^{3 V}PROG
2.2
—
3.6
V
Endurance (Write/Erase Cycles) N_WE
20k
100k
—
Cycles
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator has a programmable output frequency using the HFO0CAL register, which is factory pro-
grammed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or
erase operation. It is recommended to write the HFO0CAL register back to its reset value when writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (V_VDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
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