EFM8BB1 Datasheet, PDF (39/46 Pages) Silicon Laboratories – The EFM8BB1 highlighted features are listed below

EFM8BB1 Data Sheet
QFN20 Package Specifications
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05 mm.
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on
the pad, which is optimum to assure correct component stand-off.
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8.3 QFN20 Package Marking
PPPP
PPPP
TTTTTT
YYWW #
Figure 8.3. QFN20 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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