SI86XX Datasheet, PDF (31/52 Pages) Silicon Laboratories – No start-up initialization required

Si86xx
Table 13. Enable Input Truth¹
P/N
Si861x/2x
Si8630
Si8631
Si8640
Si8641
Si8642
Si8650
Si8651
Si8652
Si866x
EN1^1,2
—
—
—
H
L
X
X
—
—
H
L
X
X
H
L
X
X
—
—
H
L
X
X
H
L
X
X
—
EN2^1,2
Operation
— Outputs are enabled and follow input state.
H Outputs B1, B2, B3 are enabled and follow input state.
L Outputs B1, B2, B3 are disabled and in high impedance state.³
X Output A3 enabled and follows input state.
X Output A3 disabled and in high impedance state.³
H Outputs B1, B2 are enabled and follow input state.
L Outputs B1, B2 are disabled and in high impedance state.³
H Outputs B1, B2, B3, B4 are enabled and follow the input state.
L Outputs B1, B2, B3, B4 are disabled and in high impedance state.³
X Output A4 enabled and follows the input state.
X Output A4 disabled and in high impedance state.³
H Outputs B1, B2, B3 are enabled and follow the input state.
L Outputs B1, B2, B3 are disabled and in high impedance state.³
X Outputs A3 and A4 are enabled and follow the input state.
X Outputs A3 and A4 are disabled and in high impedance state.³
H Outputs B1 and B2 are enabled and follow the input state.
L Outputs B1 and B2 are disabled and in high impedance state.³
H Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
state.³
X Output A5 enabled and follow input state.
X Output A5 disabled and in high impedance state.³
H Outputs B1, B2, B3, B4 are enabled and follow input state.
L Outputs B1, B2, B3, B4 are disabled and in high impedance state.³
X Outputs A4 and A5 are enabled and follow input state.
X Outputs A4 and A5 are disabled and in high impedance state.³
H Outputs B1, B2, B3 are enabled and follow input state.
L Outputs B1, B2, B3 are disabled and in high impedance state.³
— Outputs are enabled and follow input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 2 µA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si86xx is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
Rev. 1.0
31