SI5356A Datasheet, PDF (21/29 Pages) Silicon Laboratories – IC PROGRAMMABLE, ANY-FREQUENCY 1–200 MHZ, QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5356A
Table 8. Si5356 Pin Descriptions (Continued)
5 SSC_DIS I ^{Spread Spectrum Disable.}
This pin allows disabling of the spread spectrum feature on the output clocks. Note that
the maximum voltage level on this pin must not exceed 1.3 V. To disable spread spec-
trum connect this pin to a voltage of 0.85 to 1.3 V. Connect to GND to enable spread
spectrum. A resistor voltage divider is recommended when controlled by a signal
greater than 1.3 V. See the Typical Application Circuit for details.
6
OEB
I ^{Output Enable (Active Low).}
This pin allows disabling the output clocks. Note that the maximum voltage level on this
pin must not exceed 1.3 V. To disable all outputs connect this pin to a voltage of 0.85 to
1.3 V. Connect to GND to enable all outputs. A resistor voltage divider is recommended
when controlled by a signal greater than 1.3 V. See the Typical Application Circuit for
details.
7
VDD VDD ^{Core Supply Voltage.}
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should
be located very close to this pin.
8
INTR
O ^Interrupt.
A typical pullup resistor of 1–4 k should be used on this pin.
This pin functions as an maskable interrupt output.
0 = No interrupt
1 = Interrupt present
This pin is open drain and requires an external >1 k pullup resistor.
9
CLK7
O Output Clock 7.
CMOS output clock. If unused, this pin must be left floating.
10
CLK6
O Output Clock 6.
CMOS output clock. If unused, this pin must be left floating.
11 VDDOD VDD Clock Output Bank D Supply Voltage.
Power supply for clock outputs 6 and 7. May be operated from a 1.8, 2.5, or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK6/7 are not
used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 V.
12
SCL
I I²C Serial Clock Input (3.3 V Tolerant).
13
CLK5
O ^{Output Clock 5.}
CMOS output clock. If unused, this pin must be left floating.
14
CLK4
O ^{Output Clock 4.}
CMOS output clock. If unused, this pin must be left floating.
15 VDDOC VDD ^{Clock Output Bank C Supply Voltage.}
Power supply for clock outputs 4 and 5. May be operated from a 1.8, 2.5 or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK4/5 are not
used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 V.
16 VDDOB VDD ^{Clock Output Bank B Supply Voltage.}
Power supply for clock outputs 2 and 3. May be operated from a 1.8, 2.5, or 3.3 V sup-
ply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK2/3 are not
used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 V.
17
CLK3
O ^{Output Clock 3.}
CMOS output clock. If unused, this pin must be left floating.
Rev. 1.3
21