SI5356A Datasheet, PDF (13/29 Pages) Silicon Laboratories – IC PROGRAMMABLE, ANY-FREQUENCY 1–200 MHZ, QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5356A
Disable Outputs
Set OEB_ALL = 1; reg230[4]
Set reg241 = 0x65
Register
Map
Use ClockBuilder
Desktop v3.0 or later
Write new configuration to device
accounting for the write-allowed mask
(See AN565: Configuring the Si5356A)
Apply Soft Reset
Set SOFT_RESET = 1; reg246[1]
If using down-spread:
Set MS_RESET = 1; reg 226[2] = 1
Wait 1 ms
Set MS_RESET = 0; reg 226[2] = 0
Enable Outputs
Set OEB_ALL = 0; reg230[4]
Figure 5. I²C Programming Procedure
3.5.4. Writing a Custom Configuration to NVM
An alternative to ordering an Si5356 with a custom NVM
configuration is to use the field programming kit
(Si5338/56-PROG-EVB) to write directly to the NVM of
a "blank" Si5356. Since NVM is an OTP memory, it can
only be written once. The default configuration can be
reconfigured by writing to RAM through the I²C interface
(see “3.5.2. Creating a New Configuration for RAM”).
3.6. Output Phase Adjustment
The Si5356 has a digitally-controlled phase adjustment
feature that allows the user to adjust the phase of each
output clock in relation to the other output clocks. The
phase of each output clock can be adjusted with an
error of <20 ps over a range of ±45 ns. This feature is
available on any clock output that does not have Spread
Spectrum enabled.
3.7. CMOS Output Drivers
The Si5356 has 4 banks of outputs with each bank
comprised of 2 clocks for a total of 8 CMOS outputs per
device. By default, each bank of CMOS output clocks
are in-phase. Alternatively, each output clock can be
inverted. This feature enables each output pair to
operate as a differential CMOS clock. Each of the
output banks can operate from a different VDDO supply
(1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply
applications.
The CMOS output driver has a controlled impedance of
close to 50  which includes an internal 22  series
resistor. An external series resistor is not needed when
driving 50  traces. If higher impedance traces are used
then a series resistor may be added. A typical
configuration is shown in Figure 6.
3.8. Jitter Performance
The Si5356 provides consistently low jitter for any
combination of output frequencies. The device
leverages a low phase noise single PLL architecture
and Silicon Laboratories’ patented MultiSynth fractional
output divider technology to deliver excellent jitter
performance guaranteed across process, temperature
and voltage. The Si5356 provides superior performance
to traditional multi-PLL solutions which may suffer from
degraded jitter performance depending on frequency
plan and the number of active PLLs.
Rev. 1.3
13