SI5356A Datasheet, PDF (10/29 Pages) Silicon Laboratories – IC PROGRAMMABLE, ANY-FREQUENCY 1–200 MHZ, QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5356A
3.2. Input Configuration
The Si5356 input can be driven from either an external
crystal or a reference clock. If the crystal input option is
used, the Si5356 operates as a free-running clock
generator. In this mode of operation the device requires
a low cost 25 or 27 MHz fundamental mode crystal
connected across XA and XB as shown in Figure 1.
Given the Si5356’s frequency flexibility, the same crystal
can be reused to generate any combination of output
frequencies. Custom frequency crystals are not
required. The Si5356 integrates the crystal load
capacitors on-chip to reduce external component count.
The crystal should be placed very close to the device to
minimize stray capacitance. To ensure a stable and
accurate output frequency, the recommended crystal
specifications provided in Table 4 on page 6 must be
followed. See AN360 for additional details regarding
crystal recommendations.
XTAL
Si5356
XA
XB
Figure 1. Connecting an XTAL to the Si5356
For synchronous timing applications, the Si5356 can
lock to a 5 to 200 MHz CMOS reference clock. A typical
interface circuit is shown in Figure 2. A series
termination resistor matching the driver’s output
impedance to the impedance of the transmission line is
recommended to reduce reflections.
Rs
50
Si5356
CLKIN
Figure 2. Interfacing CMOS Reference Clocks
to the Si5356
Control input signals to SSC_DIS and OEB cannot
exceed 1.3 V yet also need to meet the VOH and VOL
specifications outlined in Table 2 on page 4. When
these inputs are driven from CMOS sources, a resistive
attenuator as shown in the Typical Application Circuits
must be used. Suggested standard 1% resistor values
for RSE and RSH, when using a CMOS source, are
given below.
CMOS Level
1.8 V
2.5 V
3.3 V
RSE ohms
1000
1960
3090
RSH ohms
1580
1580
1580
3.3. Breakthrough MultiSynth Technology
Modern timing architectures require a wide range of
frequencies which are often non-integer related.
Traditional clock architectures address this by using a
combination of single PLL ICs, 4-PLL ICs and discrete
XOs, often at the expense of BOM complexity and
power. The Si5356 use patented MultiSynth technology
to dramatically simplify timing architectures by
integrating the frequency synthesis capability of 4
phase-locked loops (PLLs) in a single device, greatly
minimizing size and power requirements versus
traditional solutions. Based on a fractional-N PLL, the
heart of the architecture is a low phase noise, high-
frequency VCO. The VCO supplies a high frequency
output clock to the MultiSynth block on each of the four
independent output paths. Each MultiSynth operates as
a high-speed fractional divider with Silicon Laboratories'
proprietary phase error correction to divide down the
VCO clock to the required output frequency with very
low jitter.
The first stage of the MultiSynth architecture is a
fractional-N divider which switches seamlessly between
the two closest integer divider values to produce the
exact output clock frequency with 0 ppm error. To
eliminate phase error generated by this process,
MultiSynth calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
Based on this architecture, each clock output can
produce any frequency from 1 to 200 MHz.
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Rev. 1.3