SI5356A Datasheet, PDF (14/29 Pages) Silicon Laboratories – IC PROGRAMMABLE, ANY-FREQUENCY 1–200 MHZ, QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5356A
3.9. Status Indicators
An open-drain interrupt pin (INTR) is available to
indicate a loss of signal (LOS) condition, a PLL loss of
lock (LOL) condition, or that the PLL is in the process of
acquiring lock (SYS_CAL). As shown in Figure 7, a
status register at address 218 is available to help
identify the exact event that caused the interrupt pin to
become active. A LOS condition occurs when there is
no clock input to the Si5356. The loss of lock algorithm
works by continuously monitoring the frequency
difference between the two inputs of the phase
frequency detector. When this frequency difference is
greater than about 1000 ppm, a loss of lock condition is
declared. Note that the VCO will track the input clock
frequency for up to approximately 25000 ppm, which
will keep the inputs to the phase frequency detector at
the same frequency until the PLL comes out of lock.
When a clock input is removed, the interrupt pin will
assert, and the clock outputs may drift up to 5%. When
the input clock is reapplied with an appropriate
frequency, the PLL will again lock.
Si5356
+1.8V, +2.5V, +3.3V
VDDOA
Bank A
CLK0
MultiSynth
CLK1
50
50
PLL
+1.8V, +2.5V, +3.3V
VDDOB
Bank B
MultiSynth
CLK2
CLK3
50
50
+1.8V, +2.5V, +3.3V
VDDOC
Bank C
MultiSynth
CLK4
CLK5
50
50
+1.8V, +2.5V, +3.3V
VDDOD
Bank D
MultiSynth
CLK6
CLK7
50
50
Figure 6. CMOS Output Driver Configuration
14
Rev. 1.3