SI5356A Datasheet, PDF (15/29 Pages) Silicon Laboratories – IC PROGRAMMABLE, ANY-FREQUENCY 1–200 MHZ, QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Si5356A
3.10. I²C Interface
The Si5356 control interface is a 2-wire bus for
bidirectional communication. The bus consists of a
bidirectional serial data line (SDA) and a serial clock
input (SCL). The device operates as a slave device on
the 2-wire bus and is compatible with I²C specifications.
Both lines must be connected to the positive supply via
an external pull-up. Standard-Mode (100 kbps) and
Fast-Mode (400 kbps) operation and 7-bit addressing
are supported as specified in the I²C-Bus Specification
standard. To accommodate multiple Si5356 devices on
the same I²C bus, the Si5356 has pin 3 as I2C_LSB.
The complete 7-bit I2C bus address for the device is
70h or 71h depending upon the state of the I2C_LSB
pin. In binary, this is written as 111 000[I2C_LSB]. See
Figure 8 for the command format for both read and write
access.
Data is always sent MSB first. Table 5 includes the AC
and DC electrical parameters for the SCL and SDA I/
Os, respectively. The timing specifications and timing
diagram for the I²C bus can be found in the I²C-Bus
Specification standard. SDA timeout support is
supported for compatibility with SMBus interfaces.
The I²C interface is 3.3 V tolerant.
The I²C bus can be operated at a bus voltage of 1.71 to
3.63 V and should have a pullup resistor as
recommended by the I²C-Bus Specification. If the I²C
bus voltage is less than 2.25 V, register 27[7] must be
set to 1.
218
LOL
LOS LOS
Clk XTAL
SYS
Cal
7
6
5
4
3
2
1
0
System Calibration
(Lock Acquisition)
Loss of Signal
XTAL Input
Loss of Signal
Clock Input
Figure 7. Status Register
Loss of Lock
Rev. 1.3
15