S-8243A Datasheet, PDF (18/34 Pages) Seiko Instruments Inc – BATTRY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.2.4_00
4. CTL pins
The S-8243 has four control pins. The CTL1 and CTL2 pins are used to control the COP and DOP pin
output voltages. CTL1 takes precedence over CTL2. CTL2 takes precedence over the battery protection
circuit. The CTL3 and CTL4 pins are used to control the VBATOUT pin output voltage.
Table 9 CTL1 and CTL2 Mode
Input
Output
CTL1 pin CTL2 pin External discharging FET External charging FET
High
High
OFF
OFF
High
Open
OFF
OFF
High
Low
OFF
OFF
Open
High
OFF
OFF
Open
Open
OFF
OFF
Open
Low
Low
Low
Low
High
Open
Low
OFF
Normal^*1
Normal^*1
OFF
OFF
OFF^*2
Normal^*1
Normal^*1
*1. States are controlled by voltage detection circuit.
*2. Off state is brought after the overcharge detection delay time t_CU.
Table 10 CTL3 and CTL4 Mode
Input
Output
CTL3 pin CTL4 pin
V_BATOUT (A series)
V_BATOUT (B series)
High
High
V1 Offset
V1 Offset
High
Open
V1×0.2 + V1 Offset
V1×0.2 + V1 Offset
High
Low
Don’t use.
V2 Offset
Open
Open^*1
High
Open^*1
Don’t use.
V2 Offset
V2×0.2 + V2 Offset
V3 Offset
Open
Low
V2×0.2 + V2 Offset
V3×0.2 + V3 Offset
Low
High
V3 Offset
V4 Offset
Low
Open
V3×0.2 + V3 Offset
V4×0.2 + V4 Offset
Low
Low
Don’t use.
Don’t use.
*1. CTL3 and CTL4 pins should be open when a microcomputer is not used.
Caution Please note unexpected behavior might occur when electrical potential difference
between the CTL pin (“L” level) and VSS is generated through the external filter (R_VSS
and C_VSS) as a result of input voltage fluctuations.
18
Seiko Instruments Inc.